The present invention relates, in particular, to a data processing circuit apparatus having a circuit core module, a controller processor unit for driving and addressing the circuit core module and a data transmission unit for transmitting data between the circuit core module and at least one external circuit module.
FIG. 2 shows a conventional data processing circuit apparatus, a circuit core module (CORE) being connected to at least one external circuit module via a data processing unit (DP) and a data interface unit (DI).
The circuit core module receives control signals for controlling, by way of example, data storage in the circuit core module and/or data read-out from the circuit core module. The circuit core module is furthermore provided with address signals for addressing the data which are stored in the circuit core module and/or the data which are to be read from the circuit core module.
Whereas the circuit core module has a high degree of parallelism when processing data, the degree of parallelism for a data processing module DP and/or a data interface module DI is reduced when transmitting the data to an external circuit module (not shown). In this case, different processing speeds in the individual modules have a considerable effect on a data transfer rate or a data interchange rate between the circuit core module and external circuit modules.
The circuit core modules, for example semiconductor circuits (chips), are conventionally fabricated and offered in different speed classes. The circuit core modules comprise, for example, memory units, preferably DRAMs (Dynamic Random Access Memory).
The higher the speeds reached by the circuit core module when processing data, the higher the price secured for the entire circuit apparatus. In this case, a decisive factor for classification into speed classes is the magnitude of a maximum applicable clock frequency at which the circuit core module is still functional.
When determining a maximum clock frequency, it is disadvantageously not so much the circuit core module as the data processing module DP and/or the data interface module DI that is/are decisive.
When producing circuit apparatuses containing, for example, memory units, it is inexpedient that no attention is paid to different speed classes. It is only during the subsequent test methods in a test apparatus that the fabricated circuit apparatus is assigned to respective speed classes so that the highest retail price can respectively be secured.
In order to solve this problem, it has been proposed to first of all fabricate the circuit apparatuses containing the circuit core module COR, the data processing module DP and the data interface module DI, then to test them with regard to different speed requirements and finally to assign the circuit apparatuses which have been tested to the respective highest speed class. This conventional method has the considerable disadvantage that it is complicated and thus cost-intensive.
Furthermore, conventional circuit apparatuses cannot be used, for example, when the data processing module and/or the data interface module is/are defective. In this case, the entire circuit apparatus must be assessed as being defective and can no longer be used in any speed class.
It is disadvantageously not possible to set the conventional circuit apparatus to different, in particular high, frequencies so that a high retail price can be secured.